1. Field of the Invention
The present invention relates to integrated circuit technology. More particularly, the present invention relates to programmable delay lines compensated for process, voltage, and temperature (PVT).
2. The Prior Art
Non-PVT compensated programmable delays are known in the art. Their use frequently results in delays that are not predictable and are thus often quite different from the ideally desired value.
PVT compensated programmable delay lines are also known in the art like, for example, U.S. Pat. No. 6,958,634 (the '634 patent) issued to Rashid. The '634 patent teaches a master analog delay-locked loop (DLL) establishing a coarse time delay unit governed by analog signals generated from a phase discriminator/charge pump/bias generator arrangement. The analog signals are then used to control a slave delay line comprised of the coarse time delay units. Multiplexers select outputs from adjacent coarse time delay units and present them to a phase interpolator to generate a fine time delay which will be equal to or in between the selected adjacent coarse time delays.
The master/slave DLL taught in the '634 patent has a number of drawbacks. First, like many analog circuits it can be harder to design and be more susceptible to noise than the equivalent digital function. Phase interpolators with good linearity characteristics can be particularly difficult to design. Second, the size of the coarse time delay unit is fixed. The '634 patent teaches using different numbers of coarse time delay units in different embodiments in applications requiring different degrees of time resolution, but a considerable degree of flexibility is lost by limiting the programmable control functionality exclusively to the slave delay line. Thirdly, by doing the critical operations in analog format, conversion back to digital signal levels can be required as shown by the box labeled CM in the various '634 figures. This introduces a non-PVT compensated delay term into the output delay that may be significant in some applications.
Another example of a PVT compensated programmable delay line of the prior art is U.S. Pat. No. 7,161,402 (the '402 patent) issued to Sompur et al. The '402 patent teaches a fairly standard double data rate memory (DDR) 90° data strobe phase shift circuit comprising a master/slave DLL with a one quarter (of the master delay) length slave delay line with the point of novelty being an optionally inserted “half-bit delay” in the slave delay line used to increase the resolution of the data strobe timing. In the embodiment shown in FIG. 6 of the '402 patent, a digital block 610 is inserted between the master DLL and the slave delay line to provide a programmable percentage adjustment to the slave delay line.
The master/slave DLL of the '402 patent is very application specific and the programmable aspect is limited to a tweak of the basic 90° phase shift that such DDR data strobe delay circuits typically provide. Like the master/slave DLL of the '634 patent, no programmable control of the master DLL is present.
Field programmable gate arrays (FPGAs) are a part of a larger class of integrated circuits known as programmable logic devices (PLDs) known in the art. FPGAs are known for their ability to implement end user specified logic functions by means of programming originally uncommitted logic and routing resources. FPGAs also have a variety of programmable clock resources available. While multiple output phase (multi-phase) phase-locked loops (PLLs) and multi-phase DLLs are present on many FPGAs for clock applications, no general purpose PVT compensated programmable delay line suitable for use with both clocks and other signals has been previously disclosed.
An end user's FPGA design is typically implemented by use of a computer program product (also known as software or, more specifically, design software) produced by the FPGA manufacturer and distributed by means of a computer-readable medium such as providing a CD-ROM to the end user or making the design software downloadable over the internet. Typically the manufacturer supplies a library of design elements as part of the computer program product. The library design elements provide a layer of insulation between the end user and the circuit details of the FPGA features (like, for example, logic modules, memory blocks and programmable delay lines) available to the end user. This makes the design software easier to use for the end user and simplifies the manufacturer's task of processing the end user's complete design by the various tools in the design software.
When persons skilled in the art speak of process, voltage and temperature compensation, it is generally understood that process is compensated for in a different manner than voltage and temperature. Typically, processing refers to the characteristics of the physical integrated circuit when fully fabricated which are typically constant or nearly so (or vary within a specified lifetime drift for certain components) for the life of the part, while voltage and temperature are operating conditions that occur at any given moment when the integrated circuit is functioning. Thus process compensation typically occurs in the design phase prior to fabrication, while the circuitry doing the voltage and temperature compensation typically responds actively to changes in voltage and temperature in an ongoing manner as the part functions.